The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Legacy single-ended sensing arrays (such as register files, read-only memories, and content addressable memories) may include multiple bitcells with read ports of the multiple bitcells coupled to a set dominant latch via merge circuitry that merges the values of the read ports. The legacy single-ended sensing arrays may include a single voltage that is supplied to the bitcells, the set dominant latch, and the merge circuitry. The voltage is required to be above a certain minimum voltage to ensure proper operation of all of the bit cells, the set dominant latch, and the merge circuitry.